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digital_clock
- 数字钟vhdl程序,能够显示年月日,时分秒,还有闰年-digital_clock.It can show the year,month,day and so on.
VHDLbasicExampleDEVELOPEMENTsoursE
- 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用,介绍如下: Chapter3:schematic和vhdl文件夹,分别是数字钟设计的原理图文件和VHDL程序; Chapter4:multiplier文件夹,串并乘法器设计程序(提示:先编译程序包); Chapter5:sci文件夹,串行通信接口设计程序; Chapter6:watchdog文件夹,看门狗设计程序; Chapter7:taxi文件夹,出租车计价器设计程序; Chapte
l602display
- 1602显示单片机与FPGA的通信!实现数字钟的功能!仅供参考!望大家多多指教-desplay1602
digital_clock
- 用于FPGA可编程逻辑器件的VHDL语言编写的6显示数字钟程序。51单片机驱动6个LED数码管。-Digital clock (VHDL language) for FPGA Development
clock
- 数字钟VHDL源程序,有仿真图,源代码-VHDL digital clock source, there are simulation plans, source code, etc.
(VHDL)clook
- 自己做的基于FPGH的数字钟实现,有调时、复位和暂停等功能。-Do their own realization of the digital clock on FPGH have stressed, the reset and pause functions.
digital_clock1
- 多功能数字钟 vhdl 具有报时功能-digital clock
VHDL
- 各种vhdl程序,包括基础程序数码管,led,串口等和综合程序数字钟等。-Vhdl various procedures, including procedures based on digital control, led, serial port and integrated programs such as digital clock and so on.
watch
- 本文件为电子设计而开发的多功能数字钟VHDL语言完整源代码 --该数字钟实现的功能有时间,秒表,闹钟,年月日的显示设置等 -This document is multi-functional electronic design and development of a complete VHDL, digital clock source code- the digital clock function can be achieved time, stopwatch, alarm clo
watch
- EDA数字钟VHDL的程序,它分多个模块进行,主要是采用VHDL语言而不是Verlog语言-the program for digital clock of EDA
eda
- 南京理工大学EDA实验多功能数字钟+闹钟+dds+am调幅。-Nanjing University of EDA test multifunction digital clock+ alarm+ dds+ am AM.
vhdl-digital
- VHD L数字钟 设计源码 包括 设计思想 设计模块 -VHD L source, including digital clock design design design module
VHDL-digital-clock-
- VHDL编写的数字钟,采用元件例化的方法,可实现调秒 调分 调时 报时 闹铃的功能 开发板使用的是EP3C16Q240C8-Digital clock written in VHDL, using the example of the way components can be adjusted to achieve sub-second tone when the alarm tone Times feature development board using EP3C16Q240C8
sunday_clock
- 数字钟 VHDL 年月日 时分秒 东北大学 EDA vhdl例程 电子设计自动化-VHDL date when the digital clock every minute routine Northeastern University Electronic Design Automation EDA vhdl
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序,比如FIFO,秒表,数字钟,七段数码管,状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
shuzhizhong(vhdl)
- 数字钟设计 计时计数器用24进制计时电路; 可手动校时,能分别进行时、分的校正; 整点报时; 选做:可设置闹时功能,当计时计到预定时间时,扬声器发出闹铃信号,闹铃时间为4s,并可提前终止闹铃。-Digital clock design
duogongnengshuzizhong
- 多功能数字钟VHDL源文件,采用动态显示方式,6个数码管-Multifunction digital clock VHDL source files, dynamic display, six digital tube
CHING
- 数字钟vhdl主要分为正常显示与报时功能-Digital clock vhdl
gcounter1
- 数字钟vhdl实现,在线测试无误,具有闹钟,对表功能-Digital clock vhdl implementation, online testing is correct, with alarm, the table function
digtal_clock
- FPGA实现数字钟VHDL语言编写,包涵整点报时,清零,调时调分等功能-FPGA digital clock VHDL language, includes the whole point timekeeping, cleared when the transfer function of adjusting grading